1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly to a method of forming a pattern in a semiconductor device using a photolithographic process.
A claim of priority is made to Korean Patent Application No. 2004-37811 filed on May 27, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Photolithographic processes are commonly used to create patterns in semiconductor devices. These patterns include, for example, trenches used to form circuits. In order to create smaller, higher performance semiconductor devices, methods for forming smaller patterns in the semiconductor devices are generally needed.
Patterns are typically formed in semiconductor devices by forming a photoresist pattern on a semiconductor substrate using a photomask and then etching the semiconductor substrate using the photoresist pattern as an etching mask. In other words, the photoresist pattern generally defines the patterns to be formed in the semiconductor substrate.
The photoresist pattern is generally formed by a thin photoresist layer to ensure that an exposure margin is large enough for the photoresist pattern to be precisely formed. Unfortunately, however, a thin photoresist pattern is generally susceptible to being etched during etching of the semiconductor substrate, thereby distorting the photoresist pattern. In addition, in the event that the semiconductor substrate contains silicon, silicon byproducts are often produced on the photoresist pattern, providing another source of distortion for the photoresist patterns. In cases where a highly precise pattern is needed for a semiconductor device, such distortion of the photoresist patterns is unacceptable.
Various efforts have been made to effectively address the distortion problems described above. For example, methods adapted to prevent distortion in photoresist patterns are disclosed in Korean Patent Applications Nos. 2000-71655 and No. 2001-26007.
A conventional method of forming a pattern in a semiconductor device 10 will now be described with reference to FIGS. 1 through 4.
Referring to FIG. 1, a lower layer 14 is formed on a semiconductor substrate 12. An upper layer 16 is formed on lower layer 14. Lower layer 14 is used as an anti-reflecting coating (ARC) film, and upper layer 16 is made of photoresist. Using a photolithographic process such as exposure and development, upper layer 16 is etched to form a pattern having openings 20 exposing lower layer 14. Using an ion implantation process involving silicon ions, a silylated layer 22 is formed on a top surface of upper layer 16 and on portions of lower layer 14 exposed through openings 20. The silicon ions are introduced by an ion implantation process rather than virtual silylation to ensure that portions of silylated layer 22 formed on lower layer 14 are formed only on exposed areas, thereby preventing a bird's beak from forming in lateral regions of openings 20. This enables images of openings 20 to be accurately copied to lower layers.
Referring to FIG. 2, upper layer 16 is removed to expose a surface 24 of lower layer 14 between remaining portions of silylated layer 22.
Referring to FIG. 3, lower layer 14 is ashed using oxygen plasma. Since silicon ions used to form silylated layer 22 react with oxygen ions to form an oxide layer, lower layer 14 is not etched beneath remaining portions of silylated layer 22. Thus, the image of the remaining portions of silylated layer 22 is copied to lower layer 14.
Referring to FIG. 4, lower layer 14 is ashed to etch exposed portions of substrate 12. The remaining portions of silylated layer 22 and lower layer 14 act as an etch-stop layer in the ashing process. Once substrate 12 is etched, the remaining portions of silylated layer 22 are removed, leaving only the remaining portions of lower layer 14 on substrate 12. The remaining portions of lower layer 14 constitute pattern elements 26 for semiconductor device 10.
According to the method described above, after forming silylated layer 22 on upper layer 16 and lower layer 14, upper layer 16 and portions of silylated layer 22 formed on upper layer 16 are removed while lower layer 14 and portions of silylated layer 22 formed on lower layer 14 are not removed. In order for this to occur, upper layer 16 must be isotropically removed using etchants that do not remove silylated layer 22. Among these etchants, those having a low etch rate with respect to lower layer 14 are generally used. Otherwise, where even a small amount of lower layer 14 is removed during the removal of upper layer 16, smaller portions of silylated layer 22 remaining on lower layer 14 may be wholly or partially separated therefrom, thus making the method somewhat unpredictable.
Because the conventional method of forming patterns in a semiconductor device does not use virtual silylation, a bird's beak does not form when silylated layer 22 is formed. Because lower layer 14 may be partially removed, however, the method is still somewhat unpredictable.